For the Ethernet (registered trademark) standards and the like, a data rate has been increased from a rate of 10 gigabits per second to a rate of 25 gigabits per second. With the increase, a data rate of a serial data transmitting circuit included in a so-called SERializer/DESerializer (SerDes) and a data rate of a serial data transmitting circuit have been increased to a rate of 25 gigabits per second.
A conventional serial data transmitting circuit is described with reference to FIGS. 1A and 1B. FIG. 1A is a diagram illustrating the conventional serial data transmitting circuit 8. FIG. 1B is a timing chart of the serial data transmitting circuit 8.
The serial data transmitting circuit 8 that outputs, as a serial signal, four digital signals input in parallel includes a ½ frequency divider 110, first to third 2:1 multiplexers 120 to 122, and a driver circuit 130. If a signal to be output is driven at a rate of 25 gigabits per second, a clock signal CK with a frequency of 12.5 GHz that corresponds to a waveform PA illustrated in FIG. 1B is provided to the ½ frequency divider 110 and the third 2:1 multiplexer 122. The ½ frequency divider 110 divides the frequency of the provided clock signal CK by 2 and provides, to each of the 2:1 multiplexers 120 and 121, a frequency-divided signal having a frequency of 6.25 GHz and corresponding to a waveform PB illustrated in FIG. 1B. The first 2:1 multiplexer 120 outputs any of first and third input digital signals Din0 and Din2 based on the frequency-divided signal provided from the ½ frequency divider 110. The digital signal output from the first 2:1 multiplexer 120 corresponds to a waveform PC illustrated in FIG. 1B. In addition, the second 2:1 multiplexer 121 outputs any of second and fourth input digital signals Din1 and Din3 based on the frequency-divided signal provided from the ½ frequency divider 110. The digital signal output from the second 2:1 multiplexer 121 corresponds to a waveform PD illustrated in FIG. 1B. Furthermore, the third 2:1 multiplexer 122 outputs a digital signal output from the first or second 2:1 multiplexer 120 or 121 at a clock frequency of 12.5 GHz in the serial data transmitting circuit 8 illustrated in FIG. 1A. The digital signal output from the third 2:1 multiplexer 122 corresponds to a waveform PE illustrated in FIG. 1B. The signal Vout output from the third 2:1 multiplexer 122 is transmitted through the driver circuit 130 to a transmission path.
In the serial data transmitting circuit 8 illustrated in FIG. 1A, the ½ frequency divider 110, the third 2:1 multiplexer 122, and the driver circuit 130 that are surrounded by a broken line represented by an arrow A operate at the high frequency of 12.5 GHz. Data rates are expected to be increased in the future. It, however, tends to become difficult to increase data rates of elements such as a transistor included in a serial data transmitting circuit. It, therefore, tends to difficult to design a serial data transmitting circuit that supports such a high data rate. With increases in data rates, power to be consumed increases. In order to reduce power to be consumed, the number of elements that operate at high speeds is requested to be reduced.
In addition, if a low-power-consumption serial data transmitting circuit is used, it is preferable that the serial data transmitting circuit be compatible with a conventional serial data transmitting circuit.
The following is a reference document.
[Document 1] Japanese Patent No. 4723029.